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机译:完全自检SHA-1和SHA-256哈希函数的体系结构的设计和实现
Cyprus Univ Technol, Elect Engn Comp Engn & Informat Dept, Limassol, Cyprus;
Antcor Adv Network Technol SA, Sorou Str 12, Athens, Greece;
Univ Patras, Dept Elect & Comp Engn, VLSI Design Lab, Patras, Greece;
European Univ Cyprus, Dept Comp Sci & Engn, Nicosia, Cyprus;
Univ Patras, Dept Elect & Comp Engn, VLSI Design Lab, Patras, Greece;
Cryptography; Hash functions; SHA-1; SHA-256; Totally Self-Checking; Concurrent Error Detection;
机译:SHA-1和SHA-256哈希函数的流水线设计的面积吞吐量折衷
机译:开发SHA-1和SHA-2加密哈希家族的完全自检体系结构的系统流程
机译:SHA-1哈希函数的高速FPGA实现
机译:关于SHA-1哈希函数的完全自检硬件设计的开发
机译:SHA-512,Whirlpool和PHASH哈希函数的FPGA设计和性能分析。
机译:一种基于混沌和安全散列SHA-256的新型图像加密算法
机译:SHA-1和SHA-256哈希功能的流水线设计的区域吞吐量权衡