A low-voltage low-power CMOS fully differential linear transconductor with mobility reduction compensation

摘要

A highly linear fully differential CMOS transconductor architecture based on flipped voltage follower (FVF) is proposed. The linearity of the proposed architecture is improved by mobility reduction compensation technique. The simulated total harmonic distortion (THD) of the proposed transconductor with 0.4V_(pp) differential input is improved from -42 dB to -55dB while operating from 1.0 V supply. As an example of the applications of the proposed transconductor, a 4th-order 5 MHz Butterworth Cm-C filter is presented. The filter has been designed and simulated in UMC 130 nm CMOS process. It achieves THD of -53 dB for 0.4V_(pp) differential input. It consumes 345 μw from 1.0 V single supply. Theoretical and simulated results are in good agreement.