Low-voltage low-power CMOS sigma-delta modulators for high-resolution A/D conversion.

摘要

In order to provide more functionality and speed in a smaller form factor, considerable effort has been devoted to the continued scaling of CMOS technologies. Moreover, the proliferation of digital mobile computing environments enabled by CMOS technology scaling has dramatically changed system design constraints. Major challenges resulting from these trends include reduced power supply voltages for device reliability, reduced power consumption requirements driven by the rapid growth of mobile applications, and the reduced intrinsic gain of MOS transistors. The increased demand for mobility often requires increased battery life for extended portability, which also motivates a reduction in supply voltage.;Supply voltage reduction and decreased transistor intrinsic gain directly impact analog-to-digital interface design, one of the most critical mixed-signal functions. The lower supply voltage reduces the available signal swing, typically increasing the analog power dissipation needed to achieve a given dynamic range (DR). Furthermore, a reduced supply voltage restricts the choice of circuit topologies due to the limited voltage headroom. Degraded transistor intrinsic gain further complicates building high-precision analog circuits. The primary objective of this research has been to investigate the methods for realizing high-precision, power-efficient CMOS analog-to-digital converters in a sub-1V environment.;In this dissertation, a low-voltage low-power sigma-delta modulator with digital-audio performance is introduced. To accommodate a 0.7-V power supply with manageable analog component constraints, input feedforward with tracking multi-bit quantization is employed. In order to achieve high precision with robust operation, a single comparator tracking multi-bit quantization approach is proposed. The resulting increase in modulator feedback timing overhead is overcome with a delayed input feedforward approach. For flicker noise reduction, chopper stabilization is used in the first stage operational amplifier. To further reduce analog power dissipation, incomplete but linear settling behavior of the first stage is explored. Low-voltage circuit techniques, such as locally bootstrapped or boosted switches, are also employed.;An experimental prototype of the proposed modulator has been integrated in a 0.18-mu m CMOS technology. The prototype achieves 100 dB of dynamic range, 100-dB peak signal-to-noise ratio (SNR) and 95-dB peak signal-to-noise-plus-distortion ratio (SNDR) for a signal bandwidth of 25 kHz, while consuming only 870-muW of total power from a 0.7-V power supply at a 5-MHz sampling rate.