A novel ultra-low-power CNTFET and 45 nm CMOS based ternary SRAM

摘要

This paper presents a CNTFET based ultra-low-power ternary SRAM design which consumes merely 66 nW of power, achieving 84-98% reduction in power consumption as compared to the other CNTFET ternary SRAM designs reported in the literature. The 6-Transistor (6T) Standard Ternary Inverter (STI) cell or the 3T-STI cell form the basic building block of the conventional SRAM cells. These conventional STI designs have an undesirable direct path between V-DD and ground during certain ternary input signals, resulting in higher power consumption. In this paper, a highly power-efficient 4T-STI based Ternary SRAM design is presented, which prevents a direct path between the power supply VDD and ground in all the possible ternary logic states.While CNTFET is preferred by many researchers around the world for low-power VLSI applications, CMOS technology is still widely used in the industry because of the availability of advanced CMOS manufacturing units. Therefore, the proposed ultra-low-power ternary SRAM design has been implemented with both 32 nm CNTFET and 45 nm CMOS devices. The performance of both the CNTFET and CMOS based ultra-low-power ternary SRAM circuits have been benchmarked with corresponding conventional SRAM circuits. The overall decrease in Power Delay Product (PDP) is 86-97% in the proposed ultra-low-power ternary 32 nm CNTFET SRAM circuit and 87-99% in the proposed 45 nm CMOS SRAM with respect to corresponding conventional ternary SRAM circuits.