Switching sequence optimization for gradient errors compensation in the current-steering DAC design

摘要

In this paper, an optimization method of switching sequence is proposed to compensate for the gradient errors in the current source array of the current-steering digital-to-analog converter. Combining the central symmetry method and the iterative method, the linear and the quadratic gradient errors in the current source arrays are all eliminated. Through the mathematical induction and MATLAB simulation, the proposed switching sequence shows that both the linear and quadratic gradient errors can be compensated. To verify the optimization method proposed, a 12-bit DAC was fabricated under the 55 nm 2.5 V CMOS process. The measured INL and DNL are bounded at 0.62LSB and 0.37LSB, respectively. The SFDR is more than 78 dB with the signal frequencies below 1 MHz and more than 66 dB in the whole Nyquist band frequency.