Development of seed layer deposition and fast copper electroplating into deep microvias for three-dimensional integration

摘要

Increasing demands for electronic devices with superior performance and functionality while reducing their sizes and weight has driven the semiconductor industry to develop towards three-dimensional integration using through a silicon via (TSV) copper interconnect. In this Letter, the key enabling technologies such as barrier and seed layers preparation by electron beam evaporation and copper fast-filling into deep microvias that are void-free are investigated. The deep vertical microvias filled by copper that are void-free are achieved by a multi-step electroplating process. Also, the resistance of single vertical TSVs is tested. Furthermore, the cross-sections and the scanning electron microscopy of vertical microvias are provided and examined.