...
首页> 外文期刊>IEEE transactions on components, packaging, and manufacturing technology. Part C, Manufacturing >Compression flow modeling of underfill encapsulants for low cost flip-chip assembly
【24h】

Compression flow modeling of underfill encapsulants for low cost flip-chip assembly

机译:用于低成本倒装芯片组装的底部填充密封剂的压缩流模型

获取原文
获取原文并翻译 | 示例
           

摘要

Flip-chip technology represents a rapidly advancing area in commercial electronics. Flip-chip on board (FCOB) technology also called direct chip attach (DCA) involves the direct interconnection of integrated circuits to low cost organic substrates. In order to ensure adequate reliability, these flip-chip assemblies undergo an underfill encapsulation process in which a polymer material is placed between the chip and the substrate. Conventional underfill processing is achieved through chip site to chip site dispensing and underfill flow via capillary action, making it a costly and time consuming process particularly as device sizes increase and standoff gaps decrease. Extensive cost modeling of conventional flip-chip process technology has shown underfill processing, cleaning, and electroplating solder bumps and substrates to be the major cost driving factors. As part of the Low Cost Next Generation Flip-Chip Processing Program, an advanced flip-chip assembly process is being developed. This process eliminates the need for time consuming capillary flow processing using a compression flow technique where the underfill is applied prior to chip placement. The innovative process integrates the chip placement and polymer underfill processes using a compression or squeeze flow technique. It results in significantly lower assembly costs and reduced cycle time. In general, the compression flow of the underfill material governs assembly yield and reliability. This paper focuses on flow simulation studies of the compression flow chip placement process. It represents a fundamental advancement in compression flow simulation of polymers in its successful application to the complex geometries and surface topologies demanded by miniaturized flip-chip assembly. Here a simulation methodology is developed and simulation studies are conducted to characterize the compression flow of the underfill, estimate required chip placement forces, evaluate the effect of underfill geometry, and assess the potential formation of voids. Results yield design guidelines that give insight into process parameters such as the limits on underfill deposition geometry and underfill viscosity and provide an initial process window.
机译:倒装芯片技术代表了商业电子领域的快速发展领域。板上倒装芯片(FCOB)技术也称为直接芯片连接(DCA),涉及集成电路与低成本有机基板的直接互连。为了确保足够的可靠性,这些倒装芯片组件经过底部填充封装工艺,其中将聚合物材料放置在芯片和基板之间。传统的底部填充处理是通过芯片位置到芯片位置的分配以及通过毛细管作用的底部填充流动来实现的,这使其成为昂贵且耗时的过程,尤其是随着器件尺寸的增加和支座间隙的减小。传统倒装芯片工艺技术的广泛成本建模显示,底部填充工艺,清洁以及电镀焊料凸块和基板是主要的成本驱动因素。作为低成本下一代倒装芯片处理程序的一部分,正在开发一种先进的倒装芯片组装工艺。此过程消除了使用压缩流技术进行耗时的毛细管流处理的需要,在压缩流技术中,在芯片放置之前先施加底部填充胶即可。创新工艺使用压缩或挤压流动技术将切屑放置和聚合物底部填充工艺整合在一起。这样可以显着降低组装成本并缩短周期时间。通常,底部填充材料的压缩流控制着装配的成品率和可靠性。本文着重于压缩流芯片放置过程的流仿真研究。它代表了聚合物压缩流动模拟的根本进步,成功地将其应用于微型倒装芯片组装所需的复杂几何形状和表面拓扑。在这里,开发了一种模拟方法,并进行了模拟研究,以表征底部填充物的压缩流,估计所需的切屑放置力,评估底部填充物几何形状的影响以及评估可能形成的空隙。结果得出了设计指南,可深入了解工艺参数(例如,底部填充沉积几何形状的限制和底部填充粘度),并提供初始的处理窗口。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号