Polycrystalline silicon wafers are widely used in Photovoltaic (PV) industry as a base material for the solar cells. The existing silicon ingot slicing methods typically provide minimum wafer thickness of 300-350 μm and a surface finish of 3-5 μm Ra while incurring considerable kerf loss of 35-40%. Consequently, efficient dicing methods need to be developed, and in the quest for developing new processes for silicon ingot slicing, the wire-EDM (electric discharge machining) is emerging as a potential process. Slicing of a 3â²â² square silicon ingot into wafers of 500 μm in thickness has been performed to study the process capability. This article analyzes the effect of processing parameters on the cutting process. The objective of the experimental study is improvement in slicing speed, minimization of kerf loss and surface roughness. A central composite design-based response surface methodology (RSM) has been used to study the slicing of polycrystalline silicon ingot via wire-EDM. A zinc-coated brass wire, 100 μm in diameter, has been used as an electrode in the slicing experiments. It has been observed that the optimal selection of the process parameters results in an increase of 40-50% in the slicing rate along with a 20% reduction in the kerf loss as compared to the conventional methods. The machined surfaces on the sliced wafer were free of micro-cracks and wire material contamination, thereby making it useful for electronic applications.View full textDownload full textKeywordskerf loss, RSM, silicon ingot, slicing speed, surface quality, wire-EDMRelated var addthis_config = { ui_cobrand: "Taylor & Francis Online", services_compact: "citeulike,netvibes,twitter,technorati,delicious,linkedin,facebook,stumbleupon,digg,google,more", pubid: "ra-4dff56cd6bb1830b" }; Add to shortlist Link Permalink http://dx.doi.org/10.1080/10910344.2012.731952
展开▼
