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机译:通过光电光谱和电表征技术在金属-半导体界面上使用介电偶极插入法测量肖特基势垒高度调整
Department of Materials Science and Engineering, University of Texas at Dallas, 800 W Campbell Rd., Richardson Texas 75080;
Department of Materials Science and Engineering, University of Texas at Dallas, 800 W Campbell Rd., Richardson Texas 75080;
Department of Materials Science and Engineering, University of Texas at Dallas, 800 W Campbell Rd., Richardson Texas 75080;
Intel Corporation, 2200 Mission College Blvd., Santa Clara, California 95054;
Department of Materials Science and Engineering, University of Texas at Dallas, 800 W Campbell Rd.,Richardson Texas 75080;
Department of Materials Science and Engineering, University of Texas at Dallas, 800 W Campbell Rd.,Richardson Texas 75080;
机译:使用原子层沉积氧化铝降低介电偶极子的肖特基势垒高度,以降低接触电阻
机译:使用高κ介电偶极子调谐机制的近带边缘肖特基势垒高度调制
机译:金属/ GaN肖特基界面的电学特性-不均匀肖特基势垒高度的影响
机译:使用介电偶极子减轻了肖特基势垒高度调整,降低了FinFET源极/漏极的接触电阻
机译:介电偶极子减轻了肖特基势垒高度调整,从而降低了接触电阻。
机译:通过低温微波退火通过掺杂剂隔离技术调整肖特基势垒高度
机译:介质盖层对少数层磷光体晶体管的影响:调整肖特基势垒高度