FPGA-Based Efficient Design Approaches for Large Size Two’s Complement Squarers

摘要

This paper presents two optimized design approaches of two’s complement large size squarers using embedded multipliers in FPGAs. The realization of one of the approaches is based on Baugh–Wooley’s algorithm and the other one is a new sign-extension technique. To achieve efficient implementation, a set of optimized schemes for the realization of multi-level additions of the partial products is proposed. The squarers are implemented for operands of sizes ranging from 20 to 128 bits targeting Xilinx’ Spartan-3 using the ISE 8.1 synthesis and implementation tool, and from 38 to 128 bits targeting Altera’s Stratix II using the Quartus II 6.0 synthesis and implementation tool. The comparisons indicate that our proposed approaches offer substantial area savings and delay reduction. Using the Baugh–Wooley-based approach, the average saving in LUTs is close to 50% with an average delay reduction in the range of 13% to 20%. With the new sign extension approach, the area saving ranges from 54% to 70%, while the delay is reduced by approximately 25%. Embedded block usage for both approaches with different tools is reduced by 38% compared with the standard schemes. Keywords Squarers - FPGA - Embedded blocks - Large size operands - Two’s complement multipliers - Sign extension - Baugh–Wooley multiplier - Karatsuba–Ofman multiplication