DG2WL: A Tool to Facilitate the High Level Synthesis of Parallel Processing Array Architectures

摘要

We present DG2VHDL, a design tool which can automatically translate abstract algorithmic descrip- tions, known as Dependence Graphs, to synthesizable VHDL models and testbenches representative of distributed memory and control processor arrays, known as Signal Flow Graphs. This translation facilitates the rapid explo- ration of the large space of available parallel architectures for a given problem and frees the designer from having to code and test separately, using a Hardware Description Language, every candidate architecture under consideration. It is shown that the quality and scalability of the automatically generated VHDL models is near optimal, in the sense that the time required to synthesize them as well as the area of the resulting hardware grows at the lowest possible rate with the problem size. This makes possible the high level synthesis of processor arrays for large size real world problems, such as the computation of the Discrete Wavelet Transform and the estimation of Higher Order Statistics, that are presented as case studies.