DOUBLE-MODE VLIW ARCHITECTURE FOR IMPARTING SOFTWARE CONTROL VARIABLE MIX OF INSTRUCTION LEVEL AND TASK LEVEL PARALLEL PROCESSING

摘要

PROBLEM TO BE SOLVED: To obtain a processor which can switch double modes of instruction level and task level parallel processes under software control by including a data register, a function device, and a program counter and allowing them to operate selectively in one of 1st and 2nd modes. ;SOLUTION: A data processor operates selectively in the 1st or 2nd mode. In the 1st mode, program instructions are executed under the control of a specific program counter by a selected data register and a device selected from away function devices S1, L1, M1, D1, S2, L2, M2, and D2. In the 2nd mode, a 1st program counter controls the execution of the program instructions by using the data registers in a 1st group and the function devices S1, L1, M1, and D1 in a 1st group and a 2nd program counter controls the execution of the program instructions by using the data registers in a 2nd separated group and the function devices S2, L2, M2, and D2 in a 2nd group.;COPYRIGHT: (C)2000,JPO