Application Domain Specific Embedded FPGAs for Flexible ISA-Extension of ASIPs

摘要

This paper presents a novel architecture combining an application specific instruction set processor (ASIP) core and an application domain specific embedded FPGAs (eFPGAs) used as flexible accelerator for the ASIP. The eFPGA is based on a parametrisable architecture template optimised for arithmetic oriented applications. It was designed as a physically optimised VLSI-macro using a flexible design methodology also sketched in this paper. Quantitative comparisons of the eFPGA with a commercial standard FPGA show significant improvements in energy, area and timing delays. Simulations of the new ASIP-eFPGA architecture have been conducted using a model based approach to evaluate its efficiency. The results show that power- and area-efficiencies similar to an FPGA can be achieved for the flexible ASIP-eFPGA while preserving the flexibility of a software programmable processor.