A Highly Utilized Hardware-Based Merge Mode Estimation with Candidate Level Parallel Execution for High-Efficiency Video Coding

摘要

The merge mode is one of the new tools adopted in high-efficiency video coding ( HEVC) to improve the inter-frame coding efficiency. The merge mode saves the bits for the motion vector (MV) by sharing the MV with neighboring blocks. Merge mode estimation (MME) is the process of finding the merge mode candidate achieving the highest compression efficiency at the cost of extensive computation. This paper tackles the intrinsic inefficiency problem of hardware-based MME and proposes a new hardware-efficient MME scheme which regulates the number of fractional estimation for merge mode candidate including vertically fractional MV. The proposed MME hardware organization in this paper features two different data paths where only one path includes a vertical interpolation filter. The proposed efficient MME scheme reduces the computational complexity of MME by regulating peak computational complexity of vertical interpolation filter. As a result, the proposed MME hardware organization saves hardware resources for vertical interpolation filter. In addition, the proposed hardware maintains high utilization by adopting adaptive candidate allocation scheme which well balances workloads between two independent data paths. Consequently, the proposed MME hardware processes 62,106 of 64 × 64 CTUs per second with a clock frequency of 400 MHz and a gate count of 460.8 K, which correspond to 23% less hardware resources and 17% higher throughput than the conventional MME hardware.