Impact of Segregation Layer on Scalability and Analog/RF Performance of Nanoscale Schottky Barrier SOI MOSFET

摘要

In this paper, the impact of segregation layer density (N_(DSL)) and length (L_(DSL)) on scalability and analog/RF performance of dopant-segregated Schottky barrier (DSSB) SOI MOSFET has been investigated in sub-30 nm regime. It has been found that, although by increasing the N_(DSL) the increased off-state leakage, short-channel effects and the parasitic capacitances limits the scalability, the reduced Schottky barrier width at source-to-channel interface improves the analog/RF figures of merit of this device. Moreover, although by reducing the L_(DSL) the increased voltage drop across the underlap length reduces the drive current, the increased effective channel length improves the scalability of this device. Further, the gain-bandwidth product in a common-source amplifier based on optimized DSSB SOI MOSFET has improved by -40% over an amplifier based on raised source/drain ultrathin-body SOI MOSFET. Thus, optimizing N_(DSL) and L_(DSL) of DSSB SOI MOSFET makes it a suitable candidate for future nanoscale analog/RF circuits