Impact Analysis of NBTI/PBTI on SRAM V_(MIN) and Design Techniques for Improved SRAM V_(MIN)

摘要

Negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) are critical circuit reliability issues in highly scaled CMOS technologies. In this paper, we analyze the impacts of NBTI and PBTI on SRAM V_(MIN), and present a design solution for mitigating the impact of NBTI and PBTI on SRAM V_(MIN). Two different types of SRAM V_(MIN) (SNM-limited V_(MIN) and time-limited V_(MIN)) are explained. Simulation results show that SNM-limited V_(MIN) is more sensitive to NBTI while time-limited V_(MIN) is more prone to suffer from PBTI effect. The proposed NBTI/PBTI-aware control of wordline pulse width and woldline voltage improves cell stability, and mitigates the V_(MIN) degradation induced by NBTI/PBTI.