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High Speed Genetic Algorithms in Quantum Logic Synthesis: Low Level Parallelization vs. Representation

机译:量子逻辑综合中的高速遗传算法:低级并行与表示

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This paper focuses on the high speed Evolutionary Algorithms (EA) for the synthesis of Quantum circuits. We present a comparative study in the Evolutionary Quantum Logic Synthesis (EQLS) using different circuits representation. In EQLS, circuits are synthesized in large number while the Evolutionary Algorithm searches for a potential solution. The speed of translating the genotype (encoded binary strings) to the phenotype (circuits) depends on how fast is the creation of the circuit functional representation and how fast this representation can be evaluated to determine its function. We present the comparison between an efficient representation of the synthesized quantum circuit as Quantum Multi-Valued Decision Diagram (QMDD) and a low level parallelized evaluation method using hardware accelerated matrix manipulation. We compare the circuit representation's computation speed as well as the used computational resources on various steps of the overall design of the circuit. As it is shown in the experiments, each approach has its advantages and limitations, and an appropriate choice of each of them yields better results for a subset of the Quantum Logic synthesis (QLS) problems.
机译:本文重点介绍用于量子电路合成的高速进化算法(EA)。我们使用不同的电路表示形式在进化量子逻辑综合(EQLS)中进行比较研究。在EQLS中,电路大量合成,而进化算法则寻找潜在的解决方案。将基因型(编码的二进制字符串)转换为表型(电路)的速度取决于电路功能表示的创建速度以及可以评估该表示以确定其功能的速度。我们介绍了作为量子多值决策图(QMDD)的合成量子电路的有效表示与使用硬件加速矩阵操作的低级并行评估方法之间的比较。我们在电路整体设计的各个步骤上比较电路表示的计算速度以及所用的计算资源。如实验所示,每种方法都有其优点和局限性,对于量子逻辑综合(QLS)问题的子集,对每种方法的适当选择都会产生更好的结果。

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