Ultra-Low Power Hybrid PLL Frequency Synthesizer with Lock Check Provisioning Efficient Phase Noise

摘要

An accurate frequency synthesizer is essential in wireless communications, radar systems, and frequency metrology. However, open-loop signal sources exhibit severe frequency fluctuation and are vulnerable to supply-induced frequency drift, phase noise, power consumption. There is a demand for precise oscillation frequency with wide tuning range and low phase noise. This motivates the proposed synthesizer to achieve relatively lower in-band phase noise as well as good out-of-band phase noise through the use of digital amplitude control circuit. This paper presents a low power, low phase noise, and fast locking CMOS PLL frequency synthesizer. The frequency synthesizer is designed by using the 65nmCMOS technology. It can support LTE, GSM/EDGE application with the frequency ranged from 4.39 GHz to 5.71 GHz for the local oscillator in the RF front-end circuits. This paper achieves the faster locking with the lock check through controlling the phase detector and charge pump to enhance the locking speed of the proposed PLL. By implementing the proposed design, the locking speed can be enhanced along with minimum power consumption and phase noise.