A High Performance Hardware Architecture of H.264/AVC Fractional Motion Estimation

摘要

High-efficiency VLSI architecture based on data route and synchronous interpolation methodology for H.264/AVC fractional motion estimation is proposed in this paper. Data obtained from interpolation on-line are allocated to the next pipeline element, half-pixel and quarter-pixel matching circuit is time sharing multiplexed, bandwidth requirement is reduced, data throughput is improved, and hardware cost is saved effectively. The designs are implemented with 0.13 μm CMOS technology, experimental results show that the throughput of the proposed architecture can meet the speed requirements of real-time high-definition video encoding at the clock frequency of 300 MHz.