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机译:功率约束下3D堆叠芯片的调度测试
Department of Computer and Information Science, Linköping University, 581 83, Linköping, Sweden;
Department of Computer and Information Science, Linköping University, 581 83, Linköping, Sweden;
Department of Computer and Information Science, Linköping University, 581 83, Linköping, Sweden;
Power constrained test scheduling; 3D integration;
机译:功率约束下的3D堆叠芯片的调度测试
机译:具有堆叠式片上网络的3D IC的基于组播的测试和热感知测试计划
机译:基于遗传算法的带功率约束双速TAM的片上系统测试调度方法
机译:功率约束下的3D堆叠芯片的调度测试
机译:3D堆叠芯片新兴技术的热感知优化
机译:晶圆级底部填充对热循环测试过程中超薄芯片堆叠式3D-IC组件微凸点可靠性的影响
机译:功率约束下的3D堆叠芯片的调度测试