首页> 外文期刊>Journal of Electronic Packaging >Fabrication Steps and Thermal Modeling of Three-Dimensional Asynchronous Field Programmable Gate Array (3D-AFPGA) With Through Silicon Via and Copper Pillar Bonding Approach
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Fabrication Steps and Thermal Modeling of Three-Dimensional Asynchronous Field Programmable Gate Array (3D-AFPGA) With Through Silicon Via and Copper Pillar Bonding Approach

机译:通过硅通孔和铜柱粘接方法的三维异步场可编程门阵列(3D-AFPGA)的制造步骤和热建模

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摘要

This work will specifically detail the development of a processing and fabrication route for a three-dimensional asynchronous field-programmable gate array (3D-AFPGA) design based on an extension of pre-existing two-dimensional-field-programmable gate array (2D-FPGA) tile designs. The periodic nature of FPGAs permits the use of an alternative approach, whereby the design entails splitting the FPGA design along tile borders and inserting through silicon vias (TSVs) at regular spatial intervals. This serves to enable true 3D performance (i.e., full 3D signal routing) while leaving most of the 2D circuit layouts intact. 3D signal buffers are inserted to handle communication between vertical and adjacent neighbors. For this approach, the density of vertical interconnections was shown to be determined by the size of the bond pads used for tier-tier communications and bonding. As a consequence, reducing bond pad dimensions from 25 μm to 15 μm, or 10 μm, bond pads are preferred to increase the connectivity between layers. A 3D-AFPGA mockup test structure was then proposed for completing development and exercising the 3D integration process flows. This mockup test structure consists of a three-tier demonstration vehicle consisting of a chip-to-wafer and a subsequent chip-to-chip bond. Besides, an alternate copper bonding approach using pillars was explored. Although the intended application is for the 3D integration process compatible with the 3D AFPGA design, the test structure was also designed to be generally applicable to various applications for 3D integration. Because of the importance of thermal management of 3D-AFPGA, it is important to predict the temperature distribution and avoid the maximum junction temperature. The numerical thermal modeling for predicting the equivalent thermal conductivity in every layer and the 3D temperature distribution in the 3D-AFPGA are developed and discussed as well.
机译:这项工作将具体地详细说明基于预先存在的二维现场可编程门阵列的扩展(2D-)的三维异步现场可编程门阵列(3D-AFPGA)设计的处理和制造路由的开发FPGA)瓷砖设计。 FPGA的周期性性质允许使用替代方法,其中设计需要沿瓦片边界分割FPGA设计并以规则的空间间隔插入硅通孔(TSV)。这有助于实现真正的3D性能(即,完整的3D信号路由),同时留下大部分2D电路布局完好无损。插入3D信号缓冲器以处理垂直和相邻邻居之间的通信。对于这种方法,显示垂直互连的密度由用于层 - 层通信和键合的键合焊盘的尺寸确定。结果,减少25μm至15μm,或10μm,键合焊盘的粘接焊盘尺寸是优选增加层之间的连接。然后提出了3D-AFPGA样机测试结构,用于完成开发和锻炼3D集成过程流程。该样机测试结构包括由芯片到晶片和随后的芯片到芯片键组成的三层演示车辆。此外,探索了使用支柱的交替铜粘接方法。尽管预期的应用是用于3D AFPGA设计兼容的3D集成过程,但测试结构也被设计为通常适用于3D集成的各种应用。由于3D-AFPGA热管理的重要性,预测温度分布并避免最大结温。开发并讨论了用于预测每层中每层的等效导热率的数值热建模和3D-AFPGA中的3D温度分布。

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  • 来源
    《Journal of Electronic Packaging》 |2020年第3期|031106.1-031106.11|共11页
  • 作者单位

    Mem. ASME Engineering Department SUNY Polytechnic Institute 100 Seymour Road Utica NY 13502;

    Nanoscience Department SUNY Polytechnic Institute 257 Fuller Road Albany NY 12203;

    Engineering Department SUNY Polytechnic Institute 100 Seymour Road Utica NY 13502;

    Nanoscience Department SUNY Polytechnic Institute 257 Fuller Road Albany NY 12203;

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