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Impact of series resistance on Si nanowire MOSFET performance

机译:串联电阻对Si纳米线MOSFET性能的影响

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摘要

In gate all around (GAA) nanowire (NW) MOSFETs large series resistance due to narrow width extension regions is an important issue, playing a critical role in determining device and circuit performance. In this paper, we present a series resistance model and analyze its dependence on geometry/process parameters. The series resistance is modelled by dividing it into five resistance components namely spreading resistance, extension resistance, interface resistance, deep source-drain resistance and contact resistance. The model is validated using 3-D device simulations of 22 nm GAA devices with Source/Drain extension (SDE) length of 15 nm to 35 nm, diameter of 8 nm to 16 nm and oxide thickness of 10 A to 40 A for both n-FET and p-FET. It is found that the spreading resistance due to lateral doping gradient contributes significantly to the total series resistance. Further, the dependence of NW device performance on series resistance is quantitatively investigated with change of diameter, SDE length and Source/Drain (S/D) implantation dose. Results show a strong NW device performance dependence on S/D doping profile and extension length defining a design trade-off between Short Channel Effects (SCEs) and series resistance. It is seen that the increase in series resistance due to increase of extension length or decrease of implantation dose beyond a certain limit reduces the device drive current significantly with nearly constant OFF-state leakage current. Hence, optimization of ex-tension length and S/D implant dose is an important device design issue for sub 22 nm technology nodes.
机译:在栅极(GAA)纳米线(NW)MOSFET中,由于狭窄的宽度扩展区域而导致的大串联电阻是一个重要问题,在确定器件和电路性能方面起着至关重要的作用。在本文中,我们提出了一个串联电阻模型,并分析了其对几何/工艺参数的依赖性。通过将串联电阻分为五个电阻分量来建模,即扩展电阻,扩展电阻,界面电阻,深源漏电阻和接触电阻。使用22 nm GAA器件的3-D器件仿真对模型进行验证,对于两种n -FET和p-FET。发现由于横向掺杂梯度引起的扩展电阻对总串联电阻有很大的贡献。此外,随着直径,SDE长度和源/漏(S / D)注入剂量的变化,定量研究了NW器件性能对串联电阻的依赖性。结果表明,强大的NW器件性能取决于S / D掺杂分布和扩展长度,从而定义了短沟道效应(SCE)和串联电阻之间的设计权衡。可以看出,由于延伸长度的增加或注入剂量的减少超过一定限度而引起的串联电阻的增加,在几乎恒定的截止态泄漏电流的情况下,显着降低了器件驱动电流。因此,对于22纳米以下的技术节点,优化拉伸长度和S / D植入剂量是一个重要的设备设计问题。

著录项

  • 来源
    《Journal of Computational Electronics 》 |2013年第2期| 306-315| 共10页
  • 作者单位

    Microelectronics and VLSI, Dept. of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee 247667, India;

    Microelectronics and VLSI, Dept. of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee 247667, India;

    Microelectronics and VLSI, Dept. of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee 247667, India;

    Microelectronics and VLSI, Dept. of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee 247667, India;

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  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Gate-All-Around; Si-nanowire FET; Series resistance;

    机译:全能门;硅纳米线FET;串联电阻;

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