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机译:串联电阻对Si纳米线MOSFET性能的影响
Microelectronics and VLSI, Dept. of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee 247667, India;
Microelectronics and VLSI, Dept. of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee 247667, India;
Microelectronics and VLSI, Dept. of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee 247667, India;
Microelectronics and VLSI, Dept. of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee 247667, India;
Gate-All-Around; Si-nanowire FET; Series resistance;
机译:宽度缩放和寄生串联电阻对硅纳米MOSFET性能的影响
机译:基于射频分析的硅纳米线金属氧化物半导体场效应晶体管(MOSFET)源极和漏极串联电阻的可靠提取方法
机译:源极-漏极串联电阻对先进的全耗尽SOI n-MOSFET中漏极电流失配的影响
机译:比较电流抑制方法以增强1.2 kV SiC功率MOSFET的短路能力:使用串联连接的栅源短路Si耗尽型MOSFET的新方法与串联电阻的使用
机译:硅纳米线MOSFET及其在非易失性存储器中的应用
机译:使用双层门绝缘子在GaN-on-Si垂直沟槽MOSFET中:对性能和可靠性的影响
机译:Si基材上垂直InAs纳米线MOSFET的外在和内在性能
机译:估算mOsFET性能串联电阻影响的标准