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首页> 外文期刊>Journal of Computational Electronics >High-k dielectric materials for the gate oxide of a MIS capacitor: effect of interface states on the C-V characteristics
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High-k dielectric materials for the gate oxide of a MIS capacitor: effect of interface states on the C-V characteristics

机译:MIS电容器栅极氧化物的高k介电材料:界面状态对C-V特性的影响

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摘要

The capacitance-voltage (C-V) characteristics of metal-insulator-semiconductor (MIS) capacitors are investigated by solving in 1D the self-consistent equations using the Silvaco ATLAS device simulation package. In this paper, ambient and high temperature C-V characteristics for both positive and negative interface charge densities are studied. The results obtained from the simulation show that the C-V characteristics at ambient temperature change from high frequency to a low frequency for . We find that the shift in threshold voltage has a strong dependence on the positive and negative interface charge densities. Also, a less significant shift in threshold voltage for the highest temperature operation is found which is in the opposite direction for negative and positive interface charge densities. Electrons and holes that occupy interface traps become charged and contribute to the threshold voltage shift and a hump in the C-V characteristics.
机译:通过使用Silvaco ATLAS器件仿真软件包以一维求解自洽方程,研究了金属-绝缘体-半导体(MIS)电容器的电容-电压(C-V)特性。在本文中,研究了正负界面电荷密度的环境和高温C-V特性。从仿真获得的结果表明,环境温度下的C-V特性从变为高频率。我们发现阈值电压的变化强烈依赖于正负电荷界面密度。同样,发现最高温度操作的阈值电压变化不大,对于负和正界面电荷密度而言,方向相反。占据界面陷阱的电子和空穴带电并有助于阈值电压漂移和C-V特性的驼峰。

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