An Efficient Implementation of Low-Latency Two-Dimensional Gaussian Smoothing Filter using Approximate Carry-Save Adder

摘要

The two-dimensional Gaussian smoothing filter (2D-GSF) is one of the most useful techniques in image processing. Since the 2D-GSF requires high computational resources, its efficient design and implementation are critical in real-time processing purposes. Approximate computing is a new method that can be used to increase the performance of 2D Gaussian filter design with low computing overhead on field-programmable gate arrays (FPGAs). This study aims to provide a low-latency Gaussian filter architecture on FPGA such that it can be used in real-time processing applications. In this regard, accurate and approximate carry-save adders (CSAs) have been used in adder tree-based Gaussian filters. In our proposed method, we use two approximation steps: in the first step, we use an approximation structure named Speed-Power-Area-Accuracy for Gaussian filter design and in the second stage, we use approximate CSAs to convert adder-tree structures that are used in Gaussian filter, and as a result, we have significantly reduced the delay. The results of simulation and implementation show that the latency has reduced in a 3x 3 2D-GSF architecture up to 22% using proposed accurate CSAs and 45% using proposed approximate CSAs, compared to existing Gaussian filters with an adder tree structure.