Joint Effects of Aging and Process Variations on Soft Error Rate of Nano-Scale Digital Circuits

摘要

Soft errors have always been a concern in the design of digital circuits. As technology down-scales toward Nanometer sizes, emergence of aging effects, process variations, and Multiple Event Transients (METs) has made the soft error rate (SER) estimation of digital circuits very challenging. This paper intends to characterize the challenges by investigating the cross effects of theses issues in overall SER of a circuit. To this regard, we employ a simulation-based SER estimation approach in which the aging effect, process variations and METs are jointly considered in our fault injection process. In our simulation-based SER estimation approach, a statistical gate delay model is used. The fault injection results into ISCAS85 circuit benchmark reveal that the SER estimation without taking into account the aging effects, the process variations, and METs is significantly inaccurate.