An Ultra-Low-Power, 16 Bits CT Delta-Sigma Modulator Using 4-Bit Asynchronous SAR Quantizer for Medical Applications

摘要

In this paper, a low-power second-order feed-forward capacitor-structure continuous-time Delta Sigma modulator with a 4-bit asynchronous successive approximation register (SAR) quantizer is presented. Through the utilization capacitor structure in the proposed modulator, first, the summation node of the integrators' outputs and the feed-forward signals is implemented within the second integrator to reduce power consumption by eliminating an active summing amplifier. Second, the proposed architecture can compensate for the quantizer delay without using any excess inner digital to analog converter (DAC). In this design, the modulator applies two different low-power operational amplifiers. These advantages cause the modulator to consume very low power and achieve a favorable figure of merit (FOM) value. In fact, in this paper, the combination of the previously reported methods and designs and doing required reforms has led to a new design with better performance, especially in power reduction. The designed modulator which is simulated using 0.18 mu m CMOS technology achieves 95.98 dB peak signal-to-noise and distortion (SNDR) for 10 KHz signal bandwidth and dissipates 44 mu m while its FOM is obtained about 43 fJ/conv.-step.