Due to its advantage of quantum resistance and the provable security under some worst-case hardness assumptions, lattice-based cryptography is being increasingly researched. This paper tries to explore and present a novel lattice-based public key cryptography and its implementation of circuits. In this paper, the LWE (learning with error) cryptography is designed for circuit realization in a practical way. A strategy is proposed to dramatically reduce the stored public key size from m.(n + 1)2q to m.l.log 2q, with only several additional linear feedback shift registers. The circuit design is implemented on Xilinx Spartan-3A FPGA and performs very well with limited resources. Only 125 slices and 8 BRAMs are occupied, and there are no complex operation devices such as multipliers or dividers, all the involved arithmetic operations are additions. This design is smaller than most hardware implementations of LWE or Ring-LWE cryptography in current state, while having an acceptable frequency at 111 MHz. Therefore, LWE cryptography can be practically realized, and its advantages of quantum resistance and simple implementation make the public key cryptography promising for some applications in devices such as smart cards.
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