LOW POWER 16 X 16 BIT MULTIPLIER DESIGN USING PAL-2N LOGIC FAMILY

摘要

Multiplication plays an important role in digital signal processing. Reducing the power consumption in multipliers will bring significant power reduction to the overall digital system. (7,3) counters are one of the components that are used in parallel multipliers though it is not so popular as the (4:2) compressor. Several (7,3) counters have been reported but most of them are implemented in conventional CMOS style. In this paper, a low power (7,3) counter based on adiabatic switching principles is proposed. HSPICE simulations show that it achieves huge power savings than the static CMOS counterpart.