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RESIDUE CHECKER WITH SIGNED-DIGIT ARITHMETIC FOR ERROR DETECTION OF ARITHMETIC CIRCUITS

机译:带符号数字算术的残差检验器,用于算术电路的误差检测

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This paper presents a fast residue checker for the error detection of arithmetic circuits. The residue checker consists of a number of residue arithmetic circuits such as adders, multipliers and binary-to-residue converters based on radix-two signed-digit (SD) number arithmetic. The proposed modulo m (m = 2~p+- 1) adder is designed with a p-digit SD adder, so that the modulo m addition time is independent of the word length of operands. The modulo m multiplier and binary-to-residue number converter are constructed with a binary tree structure of the modulo m SD adders. Thus, the modulo m multiplication is performed in a time proportional to Iog_2 p and an n-bit binary number is converted into a p-digit SD residue number, n p, in a time proportional to log_2(n/p)- By using the presented residue arithmetic circuits, the error detection can be performed in real-time for a large product-sum circuit.
机译:本文提出了一种用于算法电路错误检测的快速残差检查器。残差检查器由多个残差算术电路组成,例如加法器,乘法器和基于基数两个符号数字(SD)算术的二进制至残差转换器。所提出的模m(m = 2〜p + 1)加法器设计有p位SD加法器,因此模m的加法时间与操作数的字长无关。模乘数和二进制-残数转换器是用模SD加法器的二进制树结构构造的。因此,在与Iog_2 p成正比的时间内执行模m乘法,并且在与log_2(n / p)-成正比的时间内将n位二进制数转换为p位SD残差数n p。通过使用提出的残差算术电路,可以对大型积和电路实时执行错误检测。

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