首页> 外文期刊>Journal of Circuits, Systems, and Computers >RESIDUE-WEIGHTED NUMBER CONVERSION FOR MODULI SET {2‐n-l, 2‐n + 1,2‐n + 1,2‐n} USING SIGNED-DIGIT NUMBER
【24h】

RESIDUE-WEIGHTED NUMBER CONVERSION FOR MODULI SET {2‐n-l, 2‐n + 1,2‐n + 1,2‐n} USING SIGNED-DIGIT NUMBER

机译:模块集{2-n-l,2-n + 1,2-n + 1,2-n}的残差加权数转换使用有符号数字

获取原文
获取原文并翻译 | 示例

摘要

Signed-digit number systems support carry-free, constant time addition. By introducing the signed-digit number arithmetic into a residue number system (RNS), arithmetic operations can be performed efficiently. In this paper, a new algorithm for residue-to-binary conversion for four moduli set {2‐n - 1,2‐n + 1,22‐2n + 1,2‐n} that only requires modulo 2‐4n - 1 SD number addition is proposed. This moduli set has 5n-bit dynamic range. Based on the proposed algorithm, the converters are designed with a two-level binary tree structure formed by the modulo 2‐4n - 1 SD number residue adders. Moreover, we simplify the residue adders in converters to obtain more area and time efficiency. The comparison of the converters proposed with the converter using binary arithmetic using 0.18 μm CMOS gate array technology yields reductions in delays of 44%, 60% and 75% for n = 4, n = 8 and n = 16, respectively.
机译:有符号数字系统支持无携带的恒定时间加法。通过将有符号数字算术引入残数系统(RNS),可以高效地执行算术运算。本文提出了一种新的用于四模数集{2-n-1,2-n + 1,22-2n + 1,2-n}的残基到二进制转换的算法,只需要模2−4n-1建议添加SD编号。该模数集具有5n位的动态范围。基于所提出的算法,转换器被设计为具有由2-4 n-1 SD数模加法器形成的两级二进制树结构。此外,我们简化了转换器中的残渣添加器,以提高面积和时间效率。将所提议的转换器与使用0.18μmCMOS门阵列技术的二进制算术的转换器进行比较,对于n = 4,n = 8和n = 16,延迟分别减少了44%,60%和75%。

著录项

相似文献

  • 外文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号