Automatic Generation of Schematic Diagrams in High-Level Synthesis

摘要

The automatic schematic diagram generator of BIT (ASG-BIT) discussed here is a subsystem of the VHDL high-level synthesis and mixed-level simulation system (HLS-BIT). It can abstract netlists from the result of logic synthesis and generates functionally readable and aesthetically pleasing diagrams within reasonable execution time. The partitioning, placement and routing of schematic diagram are discussed ,and some results including several diagrams generated by ASG-BIT system are presented in the finale of this paper.