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首页> 外文期刊>Journal of Applied Physics >Valence and conduction band offsets at low-ka-SiO_xC_y:H/a-SiC_xN_y:H interfaces
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Valence and conduction band offsets at low-ka-SiO_xC_y:H/a-SiC_xN_y:H interfaces

机译:低ka-SiO_xC_y:H / a-SiC_xN_y:H界面的价和导带偏移

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摘要

In order to understand the fundamental electrical leakage and reliability failure mechanisms in nano-electronic low-k dielectric/metal interconnect structures, we have utilized x-ray photoelectron spectroscopy and reflection electron energy loss spectroscopy to determine the valence and conduction band offsets present at interfaces between non-porous and porous low-k a-SiO_xC_y:H interlayer dielectrics and a-SiC_xN_y:H metal capping layers. The valence band offset for such interfaces was determined to be 2.7 ± 0.2 eV and weakly dependent on the a-SiOC:H porosity. The corresponding conduction band offset was determined to be 2.1 ± 0.2 eV. The large band offsets indicate that intra metal layer leakage is likely dominated by defects and trap states in the a-SiOC:H and a-SiCN:H dielectrics.
机译:为了了解纳米电子低k介电/金属互连结构中的基本漏电和可靠性失效机制,我们利用X射线光电子能谱和反射电子能量损失谱来确定界面处的价和导带偏移无孔和多孔的低k a-SiO_xC_y:H层间电介质和a-SiC_xN_y:H金属覆盖层之间的介电常数。此类界面的价带偏移确定为2.7±0.2 eV,并弱依赖于a-SiOC:H孔隙率。相应的导带偏移确定为2.1±0.2 eV。大的带偏移表明,内部金属层的泄漏很可能由a-SiOC:H和a-SiCN:H电介质中的缺陷和陷阱状态决定。

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  • 来源
    《Journal of Applied Physics 》 |2014年第11期| 113703.1-113703.6| 共6页
  • 作者单位

    Logic Technology Development, Intel Corporation, Hillsboro, Oregon 97124, USA;

    Logic Technology Development, Intel Corporation, Hillsboro, Oregon 97124, USA;

    Logic Technology Development, Intel Corporation, Hillsboro, Oregon 97124, USA;

    Logic Technology Development, Intel Corporation, Hillsboro, Oregon 97124, USA;

    Logic Technology Development, Intel Corporation, Hillsboro, Oregon 97124, USA;

    Ocotillo Materials Laboratory, Intel Corporation, Chandler, Arizona 85248, USA;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
  • 原文格式 PDF
  • 正文语种 eng
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