首页> 外文期刊>Japanese Journal of Applied Physics. Part 1, Regular Papers, Brief Communications & Review Papers >Modeling of Time-Dependent Defect Generation during Constant Voltage Stress for Thin Gate Oxides of Submicron Metal-Oxide-Silicon Field-Effect Transistor
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Modeling of Time-Dependent Defect Generation during Constant Voltage Stress for Thin Gate Oxides of Submicron Metal-Oxide-Silicon Field-Effect Transistor

机译:亚微米金属-氧化物-硅-场效应晶体管的薄栅极氧化物在恒定电压应力下随时间变化的缺陷生成模型

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摘要

In this study, we examined time-evolution defect generation under constant-voltage stress for a 3-nm-thick gate oxide metal-oxide-silicon field-effect transistor (MOSFET). Defect generation under the stress is related to the density of electron traps that are generated from the relaxation of strained Si-0 bonds by injection holes. The solution for the time-dependent defect generation was calculated using short-time-measured gate leakage data and analytical models. This approach was taken by fitting an effective activation energy distribution from time-evolution-degradation electrical data. We assume that the disorder-induced variations in Si-O activation energy follow a Fermi-derivative distribution. Our methodology will provide the exact and convenient method of determining the degradation of gate oxides of nano scaled complementary MOS (CMOS) devices.
机译:在这项研究中,我们研究了在恒定电压应力下,对于厚度为3 nm的栅极氧化物金属氧化物硅场效应晶体管(MOSFET)的时间演化缺陷的产生。应力下的缺陷产生与电子陷阱的密度有关,电子陷阱的密度是由注入孔使应变的Si-0键松弛而产生的。使用短时测量的栅极泄漏数据和分析模型来计算时间相关缺陷生成的解决方案。通过根据时间演化-退化电数据拟合有效的激活能量分布来采用这种方法。我们假设Si-O活化能的无序诱发变化遵循费米导数分布。我们的方法将为确定纳米级互补MOS(CMOS)器件的栅极氧化物的退化提供准确而方便的方法。

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