Triple-Gate Fin Field Effect Transistors with Fin-Thickness Optimization to Reduce the Impact of Fin Line Edge Roughness

摘要

Three-dimensional (3D) statistical simulation is presented to propose using triple-gate (TG) fin field effect transistors (FinFETs) with optimized fin-thickness (T_(si)) to reduce the fin line edge roughness (LER) effect both in the device and circuit level. The results show that ultrathin fin will lead to intolerable parameter fluctuations in 20 nm double-gate (DG) FinFETs and FinFETs static random access memory (SRAM). Increasing T_(si) can alleviate fin LER effect, but in the meantime it will exacerbate the short channel effect (SCE). TG structure can strengthen the gate controllability over the channel, thus, can suppress SCE and reduce LER effect as well. Adopting TG structure can relax the constraint of fin-thickness to half the gate length.