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首页> 外文期刊>Japanese journal of applied physics >Dual Metal/High-^ Gate-Last Complementary Metal-Oxide-Semiconductor Field-Effect Transistor with SiBN Film and Characteristic Behavior In Sub-1-nm Equivalent Oxide Thickness
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Dual Metal/High-^ Gate-Last Complementary Metal-Oxide-Semiconductor Field-Effect Transistor with SiBN Film and Characteristic Behavior In Sub-1-nm Equivalent Oxide Thickness

机译:具有SiBN膜的双金属/高栅极-后栅极互补金属氧化物半导体场效应晶体管及其在1 nm以下等效氧化物厚度的特性

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摘要

For the first time, dual metal/high-k gate-last complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs) with low-dielectric constant-material offset spacers and several gate oxide thicknesses were fabricated to improve CMOSFETs characteristics. Improvements of 23aF/μm in parasitic capacitances were confirmed with a low-dielectric-constant material, and drive current improvements were also achieved with a thin gate oxide. The drive currents at 100nA/μm off leakages in n-type metal-oxide-semiconductor (NMOS) were improved from 830 to 950μA/μm and that in p-type metal-oxide-semiconductor (PMOS) were from 405 to 450μA/μm with a reduction in gate oxide thickness. The thin gate oxide in PMOS was thinner than that in NMOS and the gate leakage was increased. However the gate leakage did not affect the off leakage below a gate length of about 44 ran. On the basis of this result, in these gate-last CMOSFETs, it is concluded that the transistors have potential for further reduction of the equivalent oxide thickness without an increase in off leakages at short gate lengths for high off leakage CMOSFETs. For low off leakage CMOSFETs, the optimization of wet process condition is needed to prevent the reduction of the 2nm HfO~2 thickness in PMOS during a wet process.
机译:首次制造了具有低介电常数材料偏移间隔物和几种栅极氧化层厚度的双金属/高k栅极最后互补金属氧化物半导体场效应晶体管(CMOSFET),以改善CMOSFET的特性。使用低介电常数材料可以确认寄生电容提高了23aF /μm,并且使用薄的栅极氧化物也实现了驱动电流的提高。 n型金属氧化物半导体(NMOS)泄漏电流为100nA /μm时的驱动电流从830提高到950μA/μm,p型金属氧化物半导体(PMOS)的驱动电流从405至450μA/μm降低栅氧化层厚度。 PMOS中的薄栅极氧化物比NMOS中的栅极氧化物薄,并且栅极泄漏增加。然而,在大约44nm的栅极长度以下,栅极泄漏不影响截止泄漏。基于该结果,可以得出结论,在这些后栅极CMOSFET中,晶体管具有进一步减小等效氧化物厚度的潜力,而对于高截止漏电CMOSFET,在较短的栅极长度下不会增加截止漏电流。对于低漏电流的CMOSFET,需要优化湿工艺条件,以防止在湿工艺期间减小PMOS中2nm HfO〜2的厚度。

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  • 来源
    《Japanese journal of applied physics》 |2011年第8issue1期|p.084201.1-084201.5|共5页
  • 作者单位

    Device Technology Department, Semiconductor Technology Development Division,Semiconductor Business Group Consumer Products and Devices Group,Sony Corporation, Atsugi, Kanagawa 243-0014, Japan;

    Device Technology Department, Semiconductor Technology Development Division,Semiconductor Business Group Consumer Products and Devices Group,Sony Corporation, Atsugi, Kanagawa 243-0014, Japan;

    Device Technology Department, Semiconductor Technology Development Division,Semiconductor Business Group Consumer Products and Devices Group,Sony Corporation, Atsugi, Kanagawa 243-0014, Japan;

    Device Technology Department, Semiconductor Technology Development Division,Semiconductor Business Group Consumer Products and Devices Group,Sony Corporation, Atsugi, Kanagawa 243-0014, Japan;

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