首页> 外文期刊>Japanese journal of applied physics >A Novel Coplanar-Waveguide Band-Pass Filter Utilizing the Inductor-Capacitor Structure in 0.18 μm Complementary Metal-Oxide-Semiconductor Technology for Millimeter-Wave Applications
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A Novel Coplanar-Waveguide Band-Pass Filter Utilizing the Inductor-Capacitor Structure in 0.18 μm Complementary Metal-Oxide-Semiconductor Technology for Millimeter-Wave Applications

机译:一种新颖的共面波导带通滤波器,利用0.18μm互补金属氧化物半导体技术中的电感电容结构,用于毫米波应用

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摘要

A low-insertion-loss V-band complementary metal-oxide-semiconductor (CMOS) band-pass filter is demonstrated. The proposed filter architecture has the following features: the low-frequency transmission-zero (ω_(z1)) and the high-frequency transmission-zero (ω_(z2)) can be tuned individually by adjusting the value of the series capacitor (C_s) and the size of the built-in inductor-capacitor (LC) resonator, respectively. The folded short-stub technique is used to reduce the chip size of the filter. To reduce the silicon substrate loss, the CMOS-process-compatible backside inductively-coupled-plasma (ICP) deep trench technology is used to selectively remove the silicon underneath the filter. After the ICP etching, the filter achieves insertion-loss (1/S_(21)) lower than 3dB over the frequency range of 46.5-85.5 GHz. The minimum insertion-loss is -1.8dB at 60GHz.
机译:演示了一种低插入损耗的V波段互补金属氧化物半导体(CMOS)带通滤波器。所提出的滤波器架构具有以下特征:可以通过调整串联电容器(C_s)的值来分别调整低频传输零(ω_(z1))和高频传输零(ω_(z2))。 )和内置电感电容(LC)谐振器的尺寸。折叠短截线技术用于减小滤波器的芯片尺寸。为了减少硅衬底的损耗,采用了CMOS工艺兼容的背面电感耦合等离子体(ICP)深沟槽技术来有选择地去除过滤器下方的硅。 ICP蚀刻后,滤波器在46.5-85.5 GHz频率范围内的插入损耗(1 / S_(21))低于3dB。 60GHz时的最小插入损耗为-1.8dB。

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  • 来源
    《Japanese journal of applied physics》 |2012年第3issue1期|p.034201.1-034201.4|共4页
  • 作者单位

    Department of Electrical Engineering, National Chi Nan University, Puli 545, Taiwan, R.O.C.;

    Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan, R.O.C.;

    Department of Electronic Engineering, Chang Gung University, Kweishan 333, Taiwan, R.O.C.;

    Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan, R.O.C.;

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