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Endurance Enhancement and High Speed Set/Reset of 50 nm Generation HfO_2 Based Resistive Random Access Memory Cell by Intelligent Set/Reset Pulse Shape Optimization and Verify Scheme

机译:通过智能设置/重置脉冲形状优化和验证方案,增强耐久性和50 nm世代基于HfO_2的电阻随机存取存储单元的高速设置/重置

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摘要

This paper proposes a verify-programming method for the resistive random access memory (ReRAM) cell which achieves a 50-times higher endurance and a fast set and reset compared with the conventional method. The proposed verify-programming method uses the incremental pulse width with turnback (IPWWT) for the reset and the incremental voltage with turnback (IVWT) for the set. With the combination of IPWWT reset and IVWT set, the endurance-cycle increases from 48 x 10~3 to 2444 x 10~3 cycles. Furthermore, the measured data retention-time after 20 x 10~3 set/reset cycles is estimated to be 10 years. Additionally, the filamentary based physical model is proposed to explain the set/reset failure mechanism with various set/reset pulse shapes. The reset pulse width and set voltage correspond to the width and length of the conductive-filament, respectively. Consequently, since the proposed IPWWT and IVWT recover set and reset failures of ReRAM cells, the endurance-cycles are improved.
机译:本文提出了一种用于电阻式随机存取存储器(ReRAM)单元的验证编程方法,与传统方法相比,该方法可实现50倍的耐久性和快速的设置与复位。所提出的验证编程方法将带回折的增量脉冲宽度(IPWWT)用于复位,将带回折的增量电压(IVWT)用于组。通过结合IPWWT重置和IVWT设置,耐久性周期从48 x 10〜3增加到2444 x 10〜3个周期。此外,在20 x 10〜3个置位/重置周期后,测得的数据保留时间估计为10年。此外,提出了基于丝状体的物理模型来解释具有各种设置/重置脉冲形状的设置/重置失败机制。复位脉冲宽度和设置电压分别对应于导电丝的宽度和长度。因此,由于提出的IPWWT和IVWT恢复了ReRAM单元的置位和复位故障,因此改善了耐久性周期。

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  • 来源
    《Japanese journal of applied physics》 |2012年第2issue2期|p.02BD07.1-02BD07.6|共6页
  • 作者单位

    Department of Electrical Engineering and Information Systems, Graduate School of Engineering,The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan;

    Department of Electrical Engineering and Information Systems, Graduate School of Engineering,The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan;

    Department of Electrical Engineering and Information Systems, Graduate School of Engineering,The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan;

    Department of Electrical Engineering and Information Systems, Graduate School of Engineering,The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan;

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