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Ultralow Contact Resistivity for a Metal/p-Type Silicon Interface by High-Concentration Germanium and Boron Doping Combined with Low-Temperature Annealing

机译:高浓度锗和硼掺杂与低温退火相结合的金属/ p型硅界面的超低接触电阻率

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摘要

A contact resistivity of 6.9 × 10~(-9) Ω·cm~2 has been obtained in an AlSi (1 wt%)-Cu (0.5 wt%) alloy/silicon system by using heavy-dose ion implantations of germanium and boron combined with low-temperature annealing. The analysis of the combined state showed that B_(12) cluster was incorporated and the supersaturation activation layer was formed into the region where germanium separated. Separated germanium is expected to have high interface state density. It is considered that this interface state density also has a Fermi level, and in order to reduce the difference from the Fermi level of the substrate, the charge moves to interface state density from the substrate. As a result, it is not based on a metallic material but a work function becomes small because pinning by which a Fermi level is fixed to interface state density occurs owing to the substrate/metal interface. It is considered to be attributable to the existence of a Ge-rich layer formed by low-temperature annealing, and a supersaturation activation layer that lowers contact resistance was formed.
机译:通过使用大剂量的锗和硼离子注入,在AlSi(1 wt%)-Cu(0.5 wt%)合金/硅系统中获得的接触电阻率为6.9×10〜(-9)Ω·cm〜2结合低温退火。结合状态的分析表明,结合了B_(12)簇,并且过饱和活化层形成在锗分离的区域中。预期分离的锗具有高界面态密度。认为该界面状态密度也具有费米能级,并且为了减小与基板的费米能级的差,电荷从基板移动到界面状态密度。结果,它不是基于金属材料而是功函数变小,因为由于基板/金属界面而发生了费米能级固定到界面态密度的钉扎。认为这归因于通过低温退火形成的富Ge层,并且形成了降低接触电阻的过饱和活化层。

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  • 来源
    《Japanese journal of applied physics》 |2013年第7issue1期|075802.1-075802.6|共6页
  • 作者单位

    Center for Semiconductor Research and Development, Semiconductor and Storage Products Company, Toshiba Corporation, Yokohama 235-8522, Japan;

    Advanced Memory Development Center, Semiconductor and Storage Products Company, Toshiba Corporation, Yokkaichi, Mie 512-8550, Japan;

    Center for Semiconductor Research and Development, Semiconductor and Storage Products Company, Toshiba Corporation, Yokohama 235-8522, Japan;

    Advanced LSI Technology Laboratories, Corporate Research and Development Center, Toshiba Corporation, Yokohama 235-8522, Japan;

    Center for Semiconductor Research and Development, Semiconductor and Storage Products Company, Toshiba Corporation, Yokohama 235-8522, Japan;

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