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A Timing-driven Pin Assignment Algorithm with Improvement of Cell Placement in Standard Cell Layout

机译:改进标准单元布局中单元布局的时序驱动引脚分配算法

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In this paper, we propose a timing-driven pin assignment algorithm with improvement of cell placement in standard cell layout. The objective of the algorithm is to minimize the channel density as well as the total wire length by assigning nets to pins of cells under the given timing constraints. The layout model assumed in this paper consists of three cell rows, and the middle cell row is the one to which the proposed algorithm is applied. If the number of possible pin assignments for each cell is bounded by some con8tant k and the cell is allowed to be moved from its original position within r cells, then the proposed algorithm can solve the problem in linear time on the number of cells in the middle cell row. The proposed algorithm can easily be extended to a heuristic pin assignment algorithm to the general standard cell layout model. Experimental results with benchmark data show the effectivenes8 of the proposed algorithm.
机译:在本文中,我们提出了一种时序驱动的引脚分配算法,该算法改进了标准单元布局中的单元放置。该算法的目的是通过在给定的时序约束下将网络分配给单元的引脚,以最小化通道密度以及总导线长度。本文假设的布局模型由三个单元行组成,中间的单元行是所提出算法的应用对象。如果每个单元的可能引脚分配的数量受某个常数k的限制,并且允许该单元从r单元内的原始位置移动,则所提出的算法可以解决线性时间中该单元中单元数量的问题。中间单元格行。所提出的算法可以很容易地扩展到普通标准单元布局模型的启发式引脚分配算法。基准数据的实验结果表明了该算法的有效性。

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