A 4-bit ultra-wideband complementary metal-oxide-semiconductor attenuator with low root-mean-square amplitude error

摘要

This article presents the 4-bit ultra-wideband complementary metal-oxide-semiconductor (CMOS) attenuator in a standard 0.18-mu m CMOS process. This design adopts switched bridge-T type topologies for each attenuation bit. Based on insertion losses and input P1-dB considerations, the circuit performances can be optimized by the proper bit ordering arrangement. Therefore, the bit ordering 0.5-4-2-1 dB is employed in the 4-bit attenuator. Moreover, series inductors are added between each bit to further improve the input and output return losses. Measured results demonstrate that the attenuation range of the circuit is 7.5 dB with 0.5 dB step and the root-mean-square (RMS) amplitude error is between 0.11 and 0.13 dB from 3.1 to 10.8 GHz. The differences between simulated and measured RMS amplitude errors are less than 0.2 dB, which demonstrates the good agreement and feasibility of the design concept. The measured input P1-dB is 15 dBm at 5 GHz and the chip area is 1.12 mm(2) including all testing pads.