机译:基于OpenCL的异构计算框架下基于FPGA的卷积神经网络加速器设计
Department of Electronic Science and Technology, Beijing Jiaotong University, Beijing China;
Department of Electronic Science and Technology, Beijing Jiaotong University, Beijing China;
Department of Electronic Engineering Tsinghua University, Beijing, China;
Department of Electronic Engineering Tsinghua University, Beijing, China;
Department of Electronic Engineering Tsinghua University, Beijing, China;
Department of Electronic Science and Technology, Beijing Jiaotong University, Beijing China;
China University of Petroleum, Beijing China;
Department of Electronic Engineering Tsinghua University, Beijing, China;
Department of Mechanical Engineering Tsinghua University, Beijing, China;
Department of Electronic Engineering Tsinghua University, Beijing, China;
机译:基于OpenCL的异构计算框架下基于FPGA的卷积神经网络加速器设计
机译:基于FPGA的卷积神经网络的加速器调查
机译:FFCONV:卷积神经网络中的快速卷积层的基于FPGA的加速器
机译:使用OpenCL在异构计算框架下在FPGA上优化卷积神经网络
机译:基于FPGA的嵌入式设备卷积神经网络的加速器
机译:基于FPGA的加速器的计算模型
机译:Systolic-CNN:用于在云/边缘计算中加速卷积神经网络推断的OpenCL定义可伸缩的运行时柔性FPGA加速器架构