Power Efficiency for Hardware/Software Partitioning with Time and Area Constraints on MPSoC

摘要

Hardware/software partitioning is a crucial step in hardware/software co-design for energy-efficient, high-performance systems. Previous research efforts mainly focused on single processor architecture. Their methods can not produce high-quality solutions to the problem of hardware/software partitioning for multiprocessor systems. In this paper, we propose two algorithms for hardware/software partitioning problem on MPSoC, to minimize power consumption with time and area constraints. The Tree_Partitioning algorithm generates optimal partitioning results for tree-structured control-flow graphs using dynamic programming. For the general partitioning problem, we propose the DAG_Partitioning algorithm to produce near optimal solution efficiently for directed-acyclic graphs. The experimental results show that our proposed algorithms outperform existing techniques for a set of benchmarks with various time and area constraints.