Impact of high-κ gate dielectric and other physical parameters on the electrostatics and threshold voltage of long channel gate-all-around nanowire transistor

摘要

High- gate-all-around structure counters the Short Channel Effect (SCEs) mostly providing excellent off-state performance, whereas high mobility III-V channel ensures better on-state performance, rendering III-V nanowire GAAFET a potential candidate for replacing the current FinFETs in microchips. In this paper, a 2D simulator for the III-V GAAFET based on self-consistent solution of Schrodinger-Poisson equation is proposed. Using this simulator, capacitance-voltage profile and threshold voltage are characterized, which reveal that gate dielectric constant () and oxide thickness do not affect threshold voltage significantly at lower channel doping. Moreover, change in alloy composition of InxGa1-xAs, channel doping, and cross-sectional area has trivial effects on the inversion capacitance although threshold voltage can be shifted by the former two. Although, channel material also affects the threshold voltage, most sharp change in threshold voltage is observed with change in fin width of the channel (0.005Vm for above 10nm fin width and 0.064Vm for sub-10nm fin width). Simulation suggests that for lower channel doping below 10(23)m(-3), fin width variation affects the threshold voltage most. Whereas when the doping is higher than 10(23)m(-3), both the thickness and dielectric constant of the oxide material have strong effects on threshold voltage (0.05Vm oxide thickness and 0.01V/per unit change in ). Copyright (c) 2014 John Wiley & Sons, Ltd.