Investigations on the physical limitation and electrostatic improvement of a gate-all-around silicon nanowire transistor with Schottky barrier source/drain

摘要

The electrostatics of Schottky barrier (SB) source/drain (S/D) silicon nanowire transistorsrn(SB-NWTs) are investigated in comparison with the conventional silicon nanowire transistorsrn(SNWTs). The SB-NWTs are found to have degraded transfer/output properties,rnunacceptably large linear-region resistance (R_(lin)) and non-uniform gate controllability in thernsub-threshold region. With low S/D Schottky barrier height and effective tunneling mass, thernelectrostatic properties of SB-NWTs can be enhanced. However, quantitative assessmentrnshows that the enhancement is limited by the fact that the sub-threshold swing of SB-NWTsrncannot prevail over that of SNWTs, and unexpected degradation in drain-induced barrierrnlowering (DIBL) as well as device scalability can be induced. It is also shown that, even underrnthe most optimized condition, the R_(lin) of SB-NWTs is still larger than that of SNWTs, if thernS/D extension (SDE) length of the standard SNWTs is designed to be short enough. It isrnshown that, from the point of electrostatic improvement, the replacement of SNWTs byrnSB-NWTs cannot be promising. The physics and effectiveness of Schottky barrier modulationrnapproaches, such as dopant segregation and Fermi-level depinning, are also discussed.