机译:CMOS电路中亚阈值泄漏电流的算法设计,软件仿真和数学建模
Department of Electronics and Communication Engineering School of Engineering Sir Padampat Singhania University Bhatewar Udaipur - 313601 Rajasthan India University School of Information Communication and Technology Guru Gobind Singh Indraprastha University Sector- 16C Dwarka Delhi - 110078 India;
University School of Information Communication and Technology Guru Gobind Singh Indraprastha University Sector - 16C Dwarka Delhi - 110078 India;
20 nm; bulk; complementary metal oxide semiconductor; CMOS; device level; leakage current; MOSFET; NMOS; subthreshold; technology computer-aided design; TCAD; very large scale integration; VLSI;
机译:具有地塌陷的电源开关:同时控制纳米级CMOS电路中的亚阈值和栅极泄漏电流
机译:CMOS电路中泄漏边界的模型和算法
机译:低压亚阈值CMOS电流模式电路:设计和应用
机译:纳米级CMOS电路中亚阈值和栅极漏电流的同时控制
机译:CMOS技术中EOS / ESD保护电路的建模仿真和设计指南
机译:基于等效电路模型的亚阈值区域CMOS太赫兹等离子体检测器的准静态分析
机译:基于紧凑电流建模精确估算缩放CmOs逻辑电路中的总漏电流