A framework for high-speed parallel-prefix adder performance evaluation and comparison

摘要

A new framework is proposed for the evaluation and comparison of high-speed parallel-prefix adders. The framework specifies input registers and latches and requires sum feedback for single cycle pipelined operation. Test pattern generation is also specified. A newly revised energy-efficient 64-bit carry select adder with distributed mixed valence logic to help reduce fan-out and wire load is presented. Footless pulsed-precharge domino and compound domino circuits, and smaller transistors help to reduce area and power. Detailed simulations with 65nm CMOS models are compared with other parallel-prefix adders that have been instantiated for comparison. Within this framework, energy reductions of 40% are obtained for the new adder versus two leading Kogge-Stone designs, and 25% versus a new constant delay logic Sklansky style design, at similar cycle times. Copyright (c) 2014 John Wiley & Sons, Ltd.