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Design of High-Speed Low-Power Parallel-Prefix VLSI Adders

机译：高速低功耗并行前缀VLSI加法器的设计

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G. Dimitrakopoulos; P. Kolovos; P. Kalogerakis; D. Nikolos;
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年度 2010
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1. Design of high-speed low-power parallel-prefix adder trees in nanometer technologies [J] . Stefania Perri, Marco Lanuzza, Pasquale Corsonello International journal of circuit theory and applications . 2014,第7期

机译：纳米技术中的高速低功耗并行前缀加法器树的设计
2. High-speed parallel-prefix VLSI Ling adders [J] . Dimitrakopoulos G., Nikolos D. IEEE Transactions on Computers . 2005,第2期

机译：高速并行前缀VLSI Ling加法器
3. Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders [J] . Cui Xiaoping, Liu Weiqiang, Wang Shumin, Journal of signal processing systems for signal, image, and video technology . 2018,第3期

机译：高速宽词混合并行前缀/运载选择和跳过加法器的设计
4. Design of High-Speed Low-Power Parallel-Prefix VLSI Adders [C] . G. Dimitrakopoulos, P. Kolovos, P. Kalogerakis, International Workshop on Integrated Circuit and System Design . 2004

机译：高速低功耗并行前缀VLSI加法器的设计
5. Low-power and high-speed algorithms and VLSI architectures for error control coding and adaptive video scaling. [D] . Raghupathy, Arun. 1998

机译：用于错误控制编码和自适应视频缩放的低功耗，高速算法和VLSI架构。
6. Two novel low-power and high-speed dynamic carbon nanotube full-adder cells [O] . Mehdi Bagherizadeh, Mohammad Eshghi 2011

机译：两个新颖的低功耗高速动态碳纳米管全加电池
7. High-Speed Parallel-Prefix VLSI Ling Adders [O] . Giorgos Dimitrakopoulos, Dimitris Nikolos 2005

机译：高速并行前缀VLsI Ling加法器
8. High-Speed and Low-Power VLSI Error Control Coders [R] . Parhi, K. K. 2004

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