P-channel logic 2 T eDRAM macro with high retention bit architecture

摘要

This study presents a novel approach which enhances the data retention capability of PMOS gain cell based embedded DRAM. The proposed circuit technique utilizes a parasitic capacitance between the cell storage node and the common n-well body. During the write operation, an up-down voltage transition to the n-well increases the cell storage retention time without using any optional devices. It also results in much high immunity against the write 1 disturbance. Measured and simulated results from an 8192-wordx8-bit eDRAM macro implemented in a 0.13-m generic CMOS process exhibit 58% increased retention time and approximately 3.6 times stronger write disturbance immunity over the conventional design.