This research addresses the problem of current estimation at a high level networks. These current estimates can be used at register transfer (RT) level to design block-level power distribution networks, and also to obtain time based true transient power. We target bottom-up current macro-modeling, which is useful when one is reusing a previously designed logic block, so that all the internal structural details of the circuit are known. In this case, one develops a current macro-model for the block that can be used to estimate the current drawn by the block without performing a more expensive transistor or gate-level simulation.; High-level current estimation capability is required to provide early warning of any top-level power distribution problems like voltage drop, electromigration before the circuit-level design has been specified. Because, by the time the design is specified at the gate or transistor levels, it may be too late and expensive to fix problems associated with the power distribution network (power grid). It may require significant redesign effort and time, to fix problems associated with the power grid.; High-level power-grid design and analysis requires a current macro-model for different logic blocks that are both easy to use and automatically constructed. The main contribution of this research is the development of current macro-models for combinational logic blocks in the frequency domain. The current waveforms obtained from the macro-models can be used to estimate energy for every input vector pair (energy per cycle) and peak-current for every input vector pair (peak current per cycle), apart from being useful in analyzing power grids the automatic construction of these macro-models based on a simple characterization flow.
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