Design trade-offs of a capacitance-to-voltage converter with a zoom-in technique for grounded capacitive sensors

摘要

This paper presents a low-power, high-precision capacitance-to-voltage converter (CVC) for grounded capacitive sensors. To measure very small capacitance variations in the presence of a large offset capacitance, a new zoom-in structure is proposed. The major non-idealities of the CVC such as the settling error, charge injection, and parasitic capacitance of the switches are minimized through an optimized design. Accordingly, it is shown that the zoom-in technique can significantly reduce many of these errors. The effect of the parasitic capacitances around the sensor capacitance is significantly reduced by using a switched-capacitor-based active-shielding technique. The interface is designed as an integrated circuit using a standard 0.18-mu m CMOS technology. Simulation results show that for a sensor capacitor with a nominal value of 10 pF, variation of only 200 fF, and parasitic capacitance of up to 20 pF, a worst-case capacitance error of 0.2 fF can be achieved by taking into account the layout mismatches and the interconnection effects. The achieved latency is 100 mu s, and the CVC consumes only 80 mu A from a 2-V power supply. The simulated input capacitance resolution for this latency is 123 aF, which is quite close to our calculated resolution (126 aF). This resolution corresponds to an energy efficiency of 9.82 pJ/Step. A temperature sweep simulation has been performed over the temperature range from -45 degrees C to 125 degrees C to demonstrate the small thermal drift of the designed circuit.